The present invention relates generally to computer memory, and more specifically, to improving the write bandwidth in a memory characterized by a variable write time.
Conventional memories such as dynamic random access memory (DRAM) and static RAM (SRAM) are characterized by a deterministic time required to perform standard operations such as a write or a read. This influences the design of the memory system, in that, knowing the sequence of write and read accesses to the memory is sufficient to knowing when each access will be completed. There are however, various possible causes of variability in the write time of a memory technology or system. For example, a phase change memory (PCM) device capable of storing multiple bits per memory cell uses iterative write techniques, which may or may not succeed and for which the time required to succeed is non-deterministic. Iterative write techniques (commonly referred to as “write-and-verify”) are used with PCMs in order to allow a controller for the memory to store a desired value with an increased accuracy, since the read operations offer a feedback mechanism that can be used to reduce errors in the writing process. Storage devices where iterative write techniques are utilized are often characterized by variable write times because the number of iterations required to perform a write may vary between memory cells. This variable nature of the write mechanism has an impact on write bandwidth if a conventional implementation designed for deterministic memories is used for the memory system.
Another example where the time to perform a write may vary between memory cells is in the case of a memory system where the maximum total power is bounded and there are several independent memory sub-arrays. In this case, each sub-array may take an unpredictable amount of time to write because it may not be allowed to write until the power budget occupation allows it.